1. Field of the Invention
The present invention relates to a control unit and a method for controlling a screen, and here particularly to a control unit and a method for reducing interference patterns in a display of an image on the screen. Particularly, the present invention relates to a method and a control unit for usage with a TFT/LCD screen.
2. Description of the Related Art
Complex systems, which use a plurality of signal, show increasing interactions between digital and analog components with increasing decrease of pattern size. This fact is serious in systems which unite several clock signals (clock domains) on one chip, and which use similar frequencies for digital data processing and analog data acquisition.
Particularly in graphic applications, such interactions show in the form of interference patterns in the output image, which will be discussed below in more detail with regard to a TFT/LSD screen (TFT=Thin Film Transistor; LCD=Liquid Crystal Display).
For connecting TFT/LCD screens to common image sources (such as to PC graphic cards: VGA, DVI and parallel ports (PC=Personal Computer; VGA=Video Graphics Adapter; DVI=Digital Video Input)), LCD control units are required, which acquire different input data, transfer them to digital RGB data (RGB=Red, Green, Blue) and output them with the waveform (pixel frequency) required by the respective screen type.
FIG. 8 shows a simplified block diagram of a conventional LCD control chip 800. The control chip 800 receives input signals from different input sources 802, 804, and 806. This is the schematically illustrated signal source 802, which provides analog video input signals (AVI=Analog Video Input). The signal source 804 provides digital video input signals (DVI=Digital Video Input). The signal source 806 provides parallel video input signals (PVI=Parallel Video Input). The input signals provided to the control chip 800 by the input sources 802 to 806 are applied to an input selection unit 808, which selects the input signals to be processed and provides them to an input 810 of the control chip 800. The signals provided at input 810 are provided to a processing unit 812, which comprises a FIFO memory (FIFO=First In First Out) and a memory element. The memory associated to the processing means 812 is connected to a memory interface 814 (MI=Memory Interface). The processing unit 812 outputs the pixel data to be displayed on the screen with a pixel frequency ppll_clk to the screen, via an output 814 and the output interface 816. The control chip 800 further comprises a configuration block 818, which is driven with a system clock sys_clk.
At the processing unit 812, the signals are applied with the clock fclk, which corresponds to the clock of input signals acquired from the input sources 802 to 806 (DV1_clk, AVI_clk, PVI_clk).
As it is illustrated in FIG. 8, apart from the different clocks (clock domains) of the input sources (AVI_clk, DV1_clk, PVI_clk) further clocks (domains) for the memory interface 814 (mpll_clk) and the screen interface 818 (ppll_clk) are provided on the control chip 800, depending on the type of control unit. Further, the system clock sys_clk is provided.
The control chip 800 shown in FIG. 8, for example, is disposed on a printed circuit board, and receives, for example, the video or graphic signals provided by a computer for rendition and display on the screen.
It is the problem of such control units that the clock signal couple into one or several inputs of the control chip via the substrate of the control chip 800 and overlay the applied signals. Thereby, interfering interference patterns are generated in the display of the data on the screen. This problem will be illustrated below with regard to the signals received at the analog input.
With regard to the different inputs of the control chip 800, it should be noted, that, theoretically, the DVI input 804 can be interfered with by the other clock signals (clock domains) via the substrate of the chip, but, for simplicity reasons, the following description is limited to the analog input 802 (AVI) as interference sink, wherein the memory and screen clock signals mpll_clk and ppll_clk are considered as interference source, which couple into the analog input AVI via the substrate of the control chip 800, which normally has a low impedance.
The simplest case of an interference in LSCD control units, which occurs often in practice, is coupling-in of an interference signal into the analog video input 802 (AVI) with the frequency of the screen clock ppll_clk (pixel frequency) and the higher harmonics of this clock, respectively. There are several possibilities how the interference signal is generated and how it gets into the low impedance substrate of the chip 800. Apart from the digital logic in the core, the input/output driver of the output interface 818 can be seen as main source for the substrates voltages.
With regard to FIG. 9, an equivalent circuit diagram of the screen interface or output interface 818 of FIG. 8 is shown. In the left portion of FIG. 9 (left of the broken line) elements of the memory chip are illustrated, and on the right side of the broken line, elements of the circuit board are illustrated.
The interface receives the pixel signals to be displayed on the screen at the driver stage 822 from output 816 with the pixel frequency of the screen ppll_clk. In the illustrated example, the driver stage 822 comprises a first field effect transistor 822a as well as a second field effect transistor 822b. The output of the driver stage 822 is connected to a pad of the control chip 800, wherein the pad has an impedance with an ohmic portion and a capacitive portion against the substrate ground, which is illustrated in FIG. 9 by the resistor R1 and the capacity C1. The control chip 800 is connected to a housing via a bond wire, to connect a pad of the control chip to a pad of the chip housing. In FIG. 9, the inductive portion L1 and the ohmic portion R2 of the impedance of the bond wire are shown.
Additionally, the capacitive, inductive and ohmic portions of the impedances of the pad and the housing with which the control chip is connected via the bonding wire, are shown as resistor R3, as inductance L2 as well as as capacities C2 and C3.
A transmission line TL is provided on the circuit board, which outputs the signal output from the control chip to another driver stage, which again passes the signal on to the screen. Similar to the driver stage 822, the driver stage 824 comprises a first field effect transistor 824a and a second field effect transistor 824b. Further, with the capacity C4, a capacity of the housing of the driver stage 824 is illustrated.
Further, in FIG. 9 the voltage uL(t) is illustrated in relation to the inductance L1, which drops across it. As discussed above, one of the main sources for the substrate voltages are the output signals of the input/output driver stage 822 of the screen interface. This interface generates very steep signals (high di/dt) across the inductances L1, L2 and resistors R1, R2, R3 of the bond wires and the pads. This leads to the fact that voltages of up to several 100 mV (uL(t)) can drop over the bond wires, which are coupled directly or indirectly into the substrate of the control chip 800 caused by the driver layout.
Another source for interferences at the analog input of the control chip 800 can be mass or supply voltage interferences (bounces), which can arise by a low or missing decoupling on the control chip in the digital core or by an insufficient guidance of the lines supplying the supply voltage (power routing).
The visible effects are very similar in both cases, and with insufficient immunity of the analog circuits (power supply ripple rejection, ground and substrate noise decoupling), these are visible in the form of high frequency quasi noise signals (with high interference frequency finterf≈avi_clk, in the form of narrow diagonal stripes and lines (½ avi_clk≧finterf≧fhorizontal) or in the form of low frequency, horizontally aligned stripes (fhorizontal≧finterf≧fvertical) with lower or higher brightness.
The appearance of the interference visible on the screen (panel) depends on the frequencies set on the control chip 800 in relation to the input clock, wherein the respective input format (active area, blanking, etc.) plays an important part.
In FIG. 10A, an example for such an interference pattern is illustrated, which has been simulated for a LCD control unit with a screen interface based on a C model. The waveform of the interference pattern illustrated in FIG. 10a corresponds mostly to the waveform to be observed in a real LCD control unit.
So far, merely LCD control units with one screen interface have been considered. Additionally, there exist LCD control units, such as the one described with reference to FIG. 8, where the memory interface 814 is also provided. In principle, the same considerations apply as above, but in LCD control units with external memory, apart from the screen interface, significantly stronger driver inputs/outputs for the memory interface exist on the control chip 800. These stronger drivers provided for the memory interface are significant for the consideration, not least due to their effect on the substrate. Normally, the data across the memory interface are clocked with a different, normally higher clock than in the screen interface. Like in the screen interface, inductive voltages are generated across the bond wires by the very steep signals (high di/dt), which are coupled into the substrate and can influence the analog circuits from there. In reality, thus, there is a frequency mixture of at least two frequencies on the substrate, which are about in the same range as the input frequency avi_clk of the signal of the considered input source 802.
If both frequencies are considered independently, a superposition of two interference patterns, as it is shown in FIG. 10B, becomes possible. Here, merely the base frequencies and not the harmonic frequency portions are considered, which themselves would lead to a differing interference pattern.
In the following, the formation of the interference patterns discussed above with regard to FIGS. 10A and 10B, will be considered in more detail. In the formation of the interference pattern, the simplified mechanism described below is taken as a basis. Starting from a real XGA input mode (XGA=Extended Graphics Adapter), the resulting interference pattern is derived computationally and illustrated graphically by considering the set pixel frequency (only the base frequency). For the following consideration, the following conditions are assumed:
Input Mode:
XGA 1024 × 768 at 75 Hz at 78.75 MHzHorizontal Back Porch:176PixelHorizontal Front Porch:112PixelVertical Back Porch:28linesVertical Front Porch:4linesScreen Setting:
XGA 1024 × 768Pixel frequency:66 MHzTherefrom, the interference frequency finterf is calculated first to:finterf=78.75 MHz−66 MHz=12.75 MHz.Therefrom, the number of interferences can be calculated per input line at the analog video input (active area+blanking), which results to:interf/line=(78.75/12.75)−1*1312=212.4190Thus, a maximum/minimum of the interference occurs periodically with a distance of:Iinterf=1312/212.4190 . . . =6.1764 . . . pixelandtinterf=(78.75 MHz)−1*6.1764 . . . =78.4313 . . . ns, respectively.
If it is assumed that in the first frame (frame; f=1), first line (n=1), the starting point t=0s is selected, then the first minimum/maximum of the interference is visible between the sixth and seventh pixel and after 78.4313 ns, respectively, and from there on, periodically (with tinterf) until the end of the line. Since the interference period normally does not fit into an input line as an integer, a remainder is left at the end of each line. The difference of (interf/line)*n to the next integer is then the respective starting value for the following line n+1. By this shift of the respective starting value with each line, a diagonal line pattern is formed, wherein the following applies:remainder{interf/line}<0,5→diagonal stripes \\\\\\\remainder{interf/line}>0,5→diagonal stripes ///////
The value after the decimal point of (interf/line)*nmax accumulating in the last line determines the starting value of the interference in the subsequent frame (f+1), wherein in most cases, an upwards or downwards shift of the diagonal lines occurs. The result is, depending on the vertical frequency of the screen, moving diagonal lines, which travel across the original image in one direction. In fixed frequency ratios, the apparent speed in the direction of this movement is constant and depends merely on the interference frequency and the waveform of the input signal at the analog video input.
The above stated explanations, which have led to the interference pattern, are summarized again graphically with reference to FIG. 11. Particularly, the fixing of the starting values is illustrated for the subsequent lines and subsequent frames.
In reality, the mechanism of the interference formation is more complex, since additionally not only all harmonic frequency portions, but also the dynamic behavior of all components on the control chip, as well as the external elements, such as the phase locked loops on the control chip, the input signal sources etc., play an important part, but in principal, however, the resulting interferences can be calculated here as well.
The correlated interference patterns on the screen generated due to the above-described mechanisms are visible for a user/viewer and thus interfering.